Modern computer processor architectures typically rely on multiple functional units to execute instructions from a computer program. An instruction or issue unit typically retrieves instructions and dispatches, or issues, the instructions to one or more execution units to handle the instructions. A typical computer processor may include, for example, a load/store unit that handles retrieval and storage of data from and to a memory, and a fixed point execution unit, or arithmetic logic unit (ALU), to handle logical and arithmetic operations.
Whereas earlier processor architectures utilized a single ALU to handle all logical and arithmetic operations, demands for increased performance necessitated the development of superscalar architectures that utilize multiple execution units to handle different types of computations. Doing so enables multiple instructions to be routed to different execution units and executed in parallel, thereby increasing overall instruction throughput.
One of the most common types of operations that can be partitioned into a separate execution unit is floating point arithmetic. Floating point calculations involve performing mathematical computations using one or more floating point values. A floating point value is typically represented as a combination of an exponent and a significand. The significand, which may also be referred to as a fraction or mantissa, represents the digits in a floating point value with a predetermined precision, while the exponent represents the relative position of the binary point for the floating point value. A floating point execution unit typically includes separate exponent and significand paths, with a series of adders incorporated into the exponent path to calculate the exponent of a floating point result, and a combination of multiplier, alignment, normalization, rounding and adder circuitry incorporated into the significand path to calculate the significand of the floating point result.
Floating point execution units may be implemented as scalar execution units or vector execution units. Scalar execution units typically operate on scalar floating point values, while vector execution units operate on vectors comprising multiple scalar floating point values. Vector floating point execution units have become popular in many 3D graphics hardware designs because much of the data processed in 3D graphics processing is readily vectorizable (e.g., coordinates of objects in space are often represented using 3 or 4 floating point values).
When a separate floating point execution unit is utilized in a computer processor, other arithmetic and logical operations are typically handled in a smaller, less complex fixed point execution unit. Fixed point arithmetic, in contrast with floating point arithmetic, presumes a fixed binary point for each fixed point value. Arithmetic operations are typically performed more quickly and with less circuitry than required for floating point execution units, with the tradeoff being reduced numerical precision. Floating point operations can also be compiled into multiple fixed point operations capable of being executed by a fixed point execution unit; however, a floating point execution unit often performs the same operations much more quickly and using less instructions, so the incorporation of a floating point execution unit into a processor often improves performance for many types of computationally-intensive workloads.
Most high performance processors have therefore migrated to an architecture in which both fixed point and floating point execution units are incorporated into the same processor, thereby enabling a processor to optimally handle different types of workloads. For other types of computer processors such as mobile processors, embedded processors, low power processors, etc., however, the inclusion of both a fixed point execution unit and floating point execution unit may be problematic, often increasing cost and requiring excessive circuitry and power consumption. In such applications, designers may opt to forego a separate floating point execution unit and rely on compilation to convert floating point operations into fixed point operations that can be executed, albeit more slowly, on a fixed point execution unit.
Therefore, a need continues to exist for supporting both fixed point and floating point operations in a computer processor with reduced cost, circuitry, power consumption and adverse impacts on performance.